Recently, flash memory has been rapidly increasing in demand in household and portable electronic devices and is highly marketable, and thus is expected to exceed the existing DRAM market around the year 2007. Also, there is a continued need for memory devices having high integration density and fast write/erase time.
The existing flash memory devices are devices having a channel formed on a silicon surface. These devices seem to reach a limit between 45-60 nm technologies depending on memory types (NOR type or NAND type), and they require a device structure which has high performance and integration density and is compatible with the existing processes.
Problems with the existing flash memory devices include: a short channel effect resulting from a decrease in gate length; the cross-talk between cells, resulting from a reduction in the interval between the cells; an increase in threshold voltage distribution, resulting from a decrease in channel area and a decrease in the area of a floating electrode; and the maintenance of thick floating electrode to maintain a coupling ratio of 0.6-0.65 or more. One of the methods capable of solving these problems is to recess a channel region.